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cpu cache explained

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For detailed specifics on CPU caching and SMP design, see Curt Schimmel's Unix Systems for Modern Architecture.

Newsgroups: comp.unix.sco.misc
From: Bela Lubkin <filbo@deepthought.armory.com>
Subject: Re: 5.0.5 MP system running slowly with 1Gb RAM
Cc: Graham Nicholls <graham@rockcons.co.uk>
Date: Fri, 10 Dec 1999 23:28:57 GMT
Message-ID: <199912101528.aa13320@deepthought.armory.com> 
References: <384EACCE.5C69F28E@rockcons.co.uk>
<2RO34.93408$7I4.2356249@news5.giganews.com>
<384FCC47.5DA50F39@aplawrence.com>
<384FF323.4383@uq.net.au>
<38504BF5.B17ABAB2@rockcons.co.uk> 
 <3850DB25.E3DAD90B@aplawrence.com> <385131EA.AC3EE945@rockcons.co.uk>

Graham Nicholls wrote:

> If it is a cache issue, then why have some respondants reported very
> good performance with MP systems with 1Gb RAM and only 256k 
> cache chips ? 

There is no linear relationship between size of cache and amount of RAM
it can cache.  This is a common misconception.

Cache designs vary greatly.  One of the design parameters is the width
of tag RAM entries.  Tag RAM entries identify, for each location in the
cache, which location in main memory is represented.

One common tag RAM width is 8 bits.  An 8-bit tag can specify one of 256
locations.  An 8-bit tag combined with a 512K direct-mapped cache could
cache 256 * 512K == 128MB of RAM.  However, most caches today are not
direct; 2-way and 4-way associative caches are more common.  An N-way
associative cache is like N direct-mapped caches of (total size/N).  So
a 512K 4-way associative cache with 8-bit tags could cache 256 * (512K /
4) == 32MB of RAM.  Such a design is improbable; it would almost
certainly be designed with wider tags.  4-way 512K with 12-bit tags
would be able to cache 2^12 * 512K / 4 == 512MB.

You didn't have a performance problem at 512MB, and you do at 1GB.  So
your cache parameters are some combination which tops out at 512MB.  We
know one parameter (512K), and we can guess the associativity (1
(direct), 2- or 4-way).  The possible combinations are:

  associativity      tag length    cache size    memory coverage
  =============      ==========    ==========    ===============
  direct-mapped          10           512K           512MB
  2-way associative      11           512K           512MB
  4-way associative      12           512K           512MB

You might be able to fix this.  Go into BIOS setup, look for "advanced
chipset setup" or whatever it offers.  See if it has a "way-ness" knob.
If so, reduce it from 4-way to 2-way, or 2-way to direct.  With the same
tag length, this should double the amount of memory covered.

The Pentium III's L2 cache is inside the CPU.  I'm not really sure
whether you get to control any of this; and if you do, I'm not sure your
BIOS setup will give you access to it.  But it's worth a try.

I tried to find documentation on cachability ranges for Intel CPUs, but
gave up after a while.  It doesn't seem to be very public information.

>Bela<

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